The present invention generally relates to a database for use in the design of an integrated circuit device and to a design method using such a database, and more particularly relates to design technology to cope with system-on-chip implementation.
A semiconductor device for an electronic unit has been fabricated until just recently by forming individual types of LSI""s such as memories and processors on respective semiconductor chips and then mounting these chips on a motherboard like a printed wiring board.
Over the past few years, however, a semiconductor device is increasingly required to reduce the overall size, weight, power dissipation and fabrication cost thereof to further broaden the industrial applicability of an electronic unit including such a device. Among other things, a consumer electronic unit for use in digital information processing has to meet all of these requirements more often than any other electronic unit. Responsive to such a demand from the electronic unit industry, the prime target of semiconductor technology is going to shift from memories to system LSI""s.
Specifically, a system LSI is a single-chip implementation including memories and various types of logic circuits on a single chip. To form a system LSI, not only the technology of forming devices like transistors with dissimilar structures on a common substrate, but also the design technology thereof should be greatly innovated.
Thus, according to a suggested technique of designing a system LSI, a database is prepared in advance to design an arbitrary block consisting of a great number of cells, each implementing a required function, e.g., a so-called xe2x80x9cfunctional blockxe2x80x9d. By using such a database, any desired system LSI can be designed as a combination of blocks.
FIG. 8 is a block diagram schematically illustrating an arrangement of a conventional system LSI. As shown in FIG. 8, the system LSI includes four blocks 11A, 11B, 11C and 11. The blocks 11A and 11B are first and second universal asynchronous receiver-transmitter (UART1 and 2) blocks, the block 11C is a direct memory access (DMA) block and the block 11D is a timer (TIM) block. Each of these blocks 11A through 11D includes: an internal controller (labeled as xe2x80x9cControl Logicxe2x80x9d) 12A, 12B, 12C or 12D; an interface circuit (xe2x80x9cHost I/Fxe2x80x9d) 13A, 13B, 13C or 13D; an FIFO memory (xe2x80x9cTX-FIFOxe2x80x9d) 14A, 14B, 14C or 14D; and a clock generator (xe2x80x9cCLKGENxe2x80x9d) 15A, 15B, 15C or 15D. All of these block components are provided as individual cells. The system LSI actually includes a great number of blocks other than those illustrated in FIG. 8, but only these four blocks 11A through 11D are illustrated in FIG. 8 for sake of simplicity.
According to the conventional design method, a specific physical structure for performing an intended function has been defined in advance for each block. Thus, in the physical design of an overall semiconductor device, only the interconnections among the blocks and peripheral circuitry have to be newly designed. In this manner, the conventional method tries to increase the design efficiency considerably.
The conventional design technique, however, has the following drawbacks. In the structure shown in FIG. 8, the FIFO memories 14A through 14D and clock generators 15A through 15D are provided for the respective blocks 11A through 11D. However, at least one of the FIFO memories 14A through 14D might be shared at least between a pair of blocks 11A, 11B, 11C, 11D. Also, a common clock signal might be applicable to all of these blocks 11A through 11D. Even so, the data defined for these blocks still should be used as it is and none of the FIFO memories 14A through 14D and clock generators 15A through 15D is omissible according to such a design method. As a result, power is dissipated in vain, structure is unnecessarily complicated and occupied area increases for nothing in such a situation.
The present inventors noticed that the root of the problems involved with the conventional block-based design method lies in that the design of a semiconductor device as a system LSI is not managed at a higher level but at a lower functional design level. An object of the present invention is providing a semiconductor device optimized to meet various requirements imposed by the electronic industry, like downsizing and reduced power dissipation, by designing the overall device at the higher specification, architectural and RT levels, while still using the design data for respective blocks.
A first exemplary method according to the present invention is adapted to design a semiconductor integrated circuit device including a plurality of blocks. The method includes the steps of: a) defining exclusive operation information among the blocks; b) defining interconnection information about a sharable resource within each said block; and c) extracting a resource sharable among the blocks based on the information about the sharable resource and the exclusive operation information among the blocks.
According to the first method, a sharable resource can be extracted easily. Thus, physical resources required can be cut down by taking advantage of the sharable resource.
In one embodiment of the present invention, the first method preferably further includes the step of d) generating interconnection information about the resource sharable among the blocks after the step c) has been performed. In such an embodiment, a semiconductor integrated circuit can be designed by using the sharable resource smoothly.
In this particular embodiment, the first method may further include the step of defining timing information about the sharable resource within each said block before the step d) is performed. In the step d), the timing information is used. In such an embodiment, more accurate interconnection information can be generated about the shared resource.
In an alternate embodiment, the first method may further include the step of e) generating interconnection information about an optimized top-level hierarchy based on the interconnection information about the resource sharable among the blocks and interconnection information about a top-level hierarchy that has been generated in advance. In such an embodiment, the overall system performance of a semiconductor integrated circuit device can be estimated more accurately. Thus, an optimum database can be selected for each block.
In another alternate embodiment, the first method may further include, before the step d) is performed, the steps of: defining a standard interface for the sharable resource; and generating information about the standard interface for the sharable resource. In the step d), the standard interface information is used. In such an embodiment, more accurate interconnection information can be generated.
A second exemplary method according to the present invention is adapted to design a semiconductor integrated circuit device including: a plurality of blocks, each consisting of a plurality of cells; and a resource shared among the blocks. The method includes the steps of: a) defining exclusive operation information among the blocks; and b) generating a signal switching control for the resource shared among the blocks based on the exclusive operation information.
According to the second method, data can be generated using the exclusive operation information such that the shared resource can be taken advantage of smoothly among the respective blocks without mutual interaction.
In one embodiment of the present invention, the second method preferably further includes the step c) of defining interconnection information about a top-level hierarchy and then generating interconnection information about an optimized top-level hierarchy after the step b) has been performed. In such an embodiment, the overall system performance of a semiconductor integrated circuit device can be estimated more accurately. Thus, an optimum database can be selected for each block.
A third exemplary method according to the present invention is adapted to design a semiconductor integrated circuit device including a plurality of blocks, each consisting of a plurality of cells. The method includes the steps of: a) defining exclusive operation information as to each functional unit within each said block; b) defining interconnection information about a top-level hierarchy; and c) generating a power management for each said block based on the exclusive operation information and the interconnection information about the top-level hierarchy.
According to the third method, the power to be consumed by each block can be estimated efficiently at a higher level by utilizing the exclusive operation information such that the resultant power dissipation can be saved.
A fourth exemplary method according to the present invention is adapted to design a semiconductor integrated circuit device including a plurality of blocks, each consisting of a plurality of cells. The method includes the steps of: a) defining exclusive operation information among the blocks; b) defining interconnection information about a top-level hierarchy; and c) generating a power management among the blocks based on the exclusive operation information and the interconnection information about the top-level hierarchy.
According to the fourth method, power to be consumed can be estimated efficiently at a higher level such that the power dissipated by the overall semiconductor integrated circuit can be saved.
A fifth exemplary method according to the present invention is adapted to design a semiconductor integrated circuit device including a plurality of blocks, each consisting of a plurality of cells. The method includes the steps of: a) defining priority-order information as to respective functional units within each said block; b) defining interconnection information about a top-level hierarchy; c) generating priority-order-controlling information for the respective blocks based on the priority-order information as to the respective functional units within each said block and the interconnection information about the top-level hierarchy; d) defining information about allowable power; and e) generating a power management based on the priority-order-controlling information for the respective blocks such that each said cell operates within a range of the allowable power defined by the allowable power information.
According to the fifth method, power management can be performed in such a manner as to save the power dissipation as much as possible, while preventing the power consumed from exceeding the maximum allowable value thereof as a result of simultaneous enablement of a plurality of functions.